Arteris Expands Multi-Die Network-on-Chip Design IP and Software

Arteris recently announced the expansion of its multi-die IP solution. The new upgrades to the company’s network-on-chip (NoC) IP library include the FlexNoC Network-on-Chip with CodaCache Last-Level Cache, the Arteris Ncore Configurable Coherent Interconnect, and the Magillem Connectivity design software.

Arteris recently announced expanded capability in its NoC IP solution. 

Arteris says these two new IP solutions and design software will improve key SoC development workflows with automation. The upgraded capability can enable high-performance, multi-die chip designs in less time and improve scalability without redesign. Arteris' NoC IP implements high-speed, chiplet-to-chiplet communications within the highest performing multi-die design topologies.

Multi-Die Chiplet Architecture

To catch up to the demands of AI and modern computing technology, developers and tool providers are increasingly relying on multi-die chiplet designs. Spreading functional blocks out to independent chiplets has a number of advantages over monolithic designs.

For one, building with proven IP blocks and proven interconnect IP technology cab reduce SoC design cycle times. Chiplets also allow specialists to design subsections, so a company that, for example, focuses on processing cores does not need to specialize in memory or IO.

Arteris NoC technology improves multi-die chiplet design. 

Monolithic chips require a greater area of silicon. A wafer defect in any part of the chip area is likely to lead to the rejection of the entire chip. In contrast, a chiplet wafer will isolate such a defect, leading to the loss of only one chiplet, delivering greater wafer yields. Breaking a large chip into chiplets and utilizing high-performance NoC IP improves the routing of power, ground, and data paths between functional areas of the SoC. 

Two Multi-Die Topologies

Multi-die architecture comes in two primary topologies: homogeneous scale-out and heterogeneous disaggregation. A homogeneous scale-out is typically used for SoCs with multiple chiplets of the same type—such as multiple processing cores or an array of memory chiplets. Arteris FlexNoC and Ncore are designed to allow significant scaling within the same basic design.

Homogeneous vs. heterogeneous chiplet topologies.

Heterogeneous topology is used when chiplets differ—for example, when a processing core die, a graphics processor die, and a memory die are combined with a NoC interconnect. Arteris designed its multi-die technology for non-coherent and coherent interconnects to allow chiplet designs to mimic monolithic performance while going past current reticle limits.

Arteris NoC IP

Arteris has built a silicon-proven high-performance NoC IP library. Its NoC non-coherent FlexNoC IP is standards-compliant and integrates with third-party die-to-die controls and PHYs.

The new Ncore NoC IP brings cache-coherent reads and writes across multiple chiplets to create the appearance of a monolithic design for application programmers.

Magillem Connectivity Solution

The Magillem Connectivity design environment delivers a system for designing with Arteris IP and integrating multi-die solutions that adhere to a number of industry interconnect standards.

Magillem Connectivity reduces multi-chip design time. 

Magillem uses a data model based on the industry standard IP-XACT. It allows IP packaging, automatic IP instantiation, and human system integration (HSI) automation. Some of its key features include:

• On-chiplet connectivity to transport critical data
  • Ncore with multi-die option; a cache-coherent NoC for chiplets
  • FlexGen/FlexNoC non-coherent NoC
• Automated IP integration and chiplet assembly
  • Magillem Connectivity for assembly
  • Magillem registers for hardware and software interfaces
• Broad standards compatibility
  • Universal Chiplet Interconnect Express (UCIe)
  • Various Arm protocols
  • PCI Express (PCIe) and common physical IP configurations
  • AMBA CXS.B interface to UCIe controller and PHY
  • MBA CXS and UCIe 1.1 IP
• Processor architecture agnostic
  • Arm, RISC-V, or other CPUs using AMBA CHI or ACE

Meeting High-Performance SoC Needs

The upgraded solution brings a new level of scalability for NoC tiling. FlexNoC and Ncore have demonstrated AI chip scaling without changing the basic design. Arteris designed the solutions for multiple chip types, including CPUs, GPUs, TPUs, NPUs, and large SoCs. Virtually all high-performance applications, such as AI, machine learning, vision, and high-performance processing, may benefit from Arteris' upgraded solution.

All images used courtesy of Arteris.